--> -->

  • <tr id='SYKazO'><strong id='SYKazO'></strong><small id='SYKazO'></small><button id='SYKazO'></button><li id='SYKazO'><noscript id='SYKazO'><big id='SYKazO'></big><dt id='SYKazO'></dt></noscript></li></tr><ol id='SYKazO'><option id='SYKazO'><table id='SYKazO'><blockquote id='SYKazO'><tbody id='SYKazO'></tbody></blockquote></table></option></ol><u id='SYKazO'></u><kbd id='SYKazO'><kbd id='SYKazO'></kbd></kbd>

    <code id='SYKazO'><strong id='SYKazO'></strong></code>

    <fieldset id='SYKazO'></fieldset>
          <span id='SYKazO'></span>

              <ins id='SYKazO'></ins>
              <acronym id='SYKazO'><em id='SYKazO'></em><td id='SYKazO'><div id='SYKazO'></div></td></acronym><address id='SYKazO'><big id='SYKazO'><big id='SYKazO'></big><legend id='SYKazO'></legend></big></address>

              <i id='SYKazO'><div id='SYKazO'><ins id='SYKazO'></ins></div></i>
              <i id='SYKazO'></i>
            1. <dl id='SYKazO'></dl>
              1. <blockquote id='SYKazO'><q id='SYKazO'><noscript id='SYKazO'></noscript><dt id='SYKazO'></dt></q></blockquote><noframes id='SYKazO'><i id='SYKazO'></i>
                • 北大核心期刊(《中文核心☉期刊要目总览》2017版)
                • 中国科技核心期刊(中国科技论文统计源期刊)
                • JST 日本科学技术振兴机构数据库(日)收录期刊

                留言板

                尊敬的读者、作者、审稿人, 关于本刊的投稿、审稿、编辑和出版的任何问题, 您可以本页〓添加留言。我们将尽快给您答复。谢谢您的支持!

                姓名
                邮箱
                手机号码
                标题
                留言内容
                验证码

                3D IC中全铜互连热应力分析

                王志敏 黄秉欢 叶贵根 李逵 巩亮

                王志敏,黄秉欢,叶贵根,等.3D IC中全铜互连热应力分析[J]. 微电子学与计算机,2023,40(1):97-104 doi: 10.19304/J.ISSN1000-7180.2022.0639
                引用本文: 王志敏,黄秉欢,叶贵根,等.3D IC中全铜互连热应力分析[J]. 微电子学与计算机,2023,40(1):97-104 doi: 10.19304/J.ISSN1000-7180.2022.0639
                WANG Z M,HUANG B H,YE G G,et al. Thermal stress analysis of all-copper interconnection in 3D IC[J]. Microelectronics & Computer,2023,40(1):97-104 doi: 10.19304/J.ISSN1000-7180.2022.0639
                Citation: WANG Z M,HUANG B H,YE G G,et al. Thermal stress analysis of all-copper interconnection in 3D IC[J]. Microelectronics & Computer,2023,40(1):97-104 doi: 10.19304/J.ISSN1000-7180.2022.0639

                3D IC中全铜互连热应力分析

                doi: 10.19304/J.ISSN1000-7180.2022.0639
                基金项目: 国家自然科学基金(11972376);山东省自然科学基金重大基础研究项目(ZR2019ZD11);山东省自然科学基金(ZR2019MA007);中央高校基本科研业务费(22CX03014A)
                详细信息
                  作者简介:

                  王志敏:男,(1996-),博士研究生. 研究方向为三维封装多场耦合

                  黄秉欢:男,(1990-),博士,讲师.研究方向为微电子器件冷却技术

                  叶贵根:男,(1983-),博士,副教授.研究方向为微电子封装

                  李逵:男,(1987-),硕士,高级工程师.研究方向为微系统结构热力学可靠性和热管理技术

                  通讯作者:

                  男,(1980-),博士,教授. 研究方向为微纳系统热管理√及多场耦合. E-mail:lgong@upc.edu.cn

                • 中图分类号: TN402

                Thermal stress analysis of all-copper interconnection in 3D IC

                • 摘要:

                  三维集成电路(Three-Dimensional Integrated Circuit,3D IC)技术相比于二维封装形式具有互连长度短、异构集成度高、功耗低以及封装尺寸小等特点. 因为铜基体具有优异的导电性、抗电迁移性和机械性能,全铜互联结构替代了焊球作为连接结构应用于3D IC中. 本文通过数值模拟研究了含有全铜互连和微流道结构的3D IC模型在循环温度载荷下的热可靠性,分析了全铜互联高度对模型内部热应力的影响. 结果表明,全铜互连部分的最大热应力与铜柱所处的空间位置相关,离模型中心越远,铜柱内的变形越大. 同时,最危险铜柱内部应力分布和变形情况表明,由于铜柱上下端面所受载荷性质不同,铜柱在热载荷作用下的Mises应力大致呈左右及上下对称分布. 这会导致铜柱的潜在失效模式是轴向压缩和剪切共同作用下的断裂或损伤. 另外,最大Mises应力随铜柱高度的增加而逐渐减小,当铜柱高度为300 μm时最大Mises应力趋于稳定,可以为全铜互连可靠性设计提供参考.

                   

                • 图 1  3D IC模型示意图

                  Figure 1.  3D IC model

                  图 2  3D IC有限元模型(1/4模型)

                  Figure 2.  The finite element model of 3D IC (1/4 model)

                  图 3  循环温度载荷(两个周期)

                  Figure 3.  The loaded temperature evolving with time (2 cycles)

                  图 4  全铜互连铜柱的网格模型

                  Figure 4.  Mesh model of copper pillars for all-copper interconnects

                  图 5  不同网格数量下的铜柱最大Mises应力

                  Figure 5.  The maximum Mises stress for different element number

                  图 6  整体模型变形量

                  Figure 6.  Deformation distribution in full model

                  图 7  铜柱内应力分布(t=100 s)

                  Figure 7.  Stress distribution in copper pillar (t=100 s)

                  图 8  A1-A2线和B1-B2线上的应力分布

                  Figure 8.  Stress distribution on lines A1-A2 and B1-B2

                  图 9  铜柱的变形图(放大30倍)

                  Figure 9.  Deformation of the copper pillar (has been magnified by 30 times)

                  图 10  危险点的应力与应变随时间变化趋势

                  Figure 10.  The evolutions of stresses, and strains at the dangerous point

                  图 11  铜柱高度对最大Mises应力的影响

                  Figure 11.  The maximum Mises stress plotted with the height of copper pillar

                  图 12  不同铜柱高度下铜柱上应力分布

                  Figure 12.  The stress distribution on the copper pillar under different copper pillar heights

                  表  1  微针鳍流道和TSV结构的几何参数

                  Table  1.   Geometry parameters of micropin-fin channel and TSV structure

                  参数符号数值/μm
                  微针鳍横向间距ST470
                  微针鳍纵向间距SL375
                  微针鳍高度Hpf230
                  微针鳍直径Dpf300
                  SiO2层厚度TSiO21
                  TSV_Cu直径DCu22.5
                  微凸点高度Hmb28
                  微凸点厚度Tmb1
                  下载: 导出CSV

                  表  2  模型材料属性

                  Table  2.   The material properties of the model

                  材料密度/
                  (kg/m3
                  弹性模量/
                  GPa
                  泊松比热膨胀系数(×10?6/K)
                  Si23301700.282.6
                  SiO22270700.160.6
                  Cu8900700.3517
                  FR-41850220.3517
                  聚氧乙烯98010.3817
                  下载: 导出CSV
                • [1] MOORE G E. Cramming more components onto integrated circuits[J]. Proceedings of the IEEE,1998,86(1):82-85. DOI: 10.1109/JPROC.1998.658762.
                  [2] LAU J H. Overview and outlook of through‐silicon via (TSV) and 3D integrations[J]. Microelectronics International,2011,28(2):8-22. DOI: 10.1108/13565361111127304.
                  [3] TUCKERMAN D B, PEASE R F W. High-performance heat sinking for VLSI[J]. IEEE Electron Device Letters,1981,2(5):126-129. DOI: 10.1109/EDL.1981.25367.
                  [4] HE A T, OSBORN T, ALLEN S A B, et al. Low-temperature bonding of copper pillars for all-copper chip-to-substrate interconnections[J]. Electrochemical and Solid-State Letters,2006,9(12):C192. DOI: 10.1149/1.2353905.
                  [5] ZHU W H, SHI L, JIANG L L, et al. Effect of intermetallic compound thickness on mechanical fatigue properties of copper pillar micro-bumps[J]. Microelectronics Reliability,2020,111:113723. DOI: 10.1016/j.microrel.2020.113723.
                  [6] LI J H, ZHANG Y X, ZHANG H L, et al. The thermal cycling reliability of copper pillar solder bump in flip chip via thermal compression bonding[J]. Microelectronics Reliability,2020,104:113543. DOI: 10.1016/j.microrel.2019.113543.
                  [7] 高红. 无铅钎料Sn-3.5Ag多轴棘轮变形与低周疲劳研究[D]. 天津: 天津大学, 2007.

                  GAO H. Multiaxial ratcheting deformation and low cycle fatigue of lead-free solder Sn-3.5Ag[D]. Tianjin: Tianjin University, 2007.
                  [8] FAN X J, RANOUTA A S. Finite element modeling of system design and testing conditions for component solder ball reliability under impact[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology,2012,2(11):1802-1810. DOI: 10.1109/TCPMT.2012.2204884.
                  [9] FAN X J, RANOUTA A S, DHIMAN H S. Effects of package level structure and material properties on solder joint reliability under impact loading[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology,2013,3(1):52-60. DOI: 10.1109/TCPMT.2012.2217744.
                  [10] FAN A, RAHMAN A, REIF R. Copper wafer bonding[J]. Electrochemical and Solid-State Letters,1999,2(10):534. DOI: 10.1149/1.1390894.
                  [11] KIM T H, HOWLADER M M R, ITOH T, et al. Room temperature Cu–Cu direct bonding using surface activated bonding method[J]. Journal of Vacuum Science & Technology A:Vacuum, Surfaces, and Films,2003,21(2):449-453. DOI: 10.1116/1.1537716.
                  [12] OSBORN T, HE A, GALIBA N, et al. All-Copper Chip-to-Substrate interconnects part I. Fabrication and characterization[J]. Journal of the Electrochemical Society,2008,155(4):D308. DOI: 10.1149/1.2839007.
                  [13] HE A, OSBORN T, ALLEN S A B, et al. All-copper chip-to-substrate interconnects Part II. Modeling and design[J]. Journal of the Electrochemical Society,2008,155(4):D314. DOI: 10.1149/1.2839014.
                  [14] OSBORN T, HE A, LIGHTSEY H, et al. All-copper chip-to-substrate interconnects: bonding, testing, and design for electrical performance and thermo-mechanical reliability[C]//2008 58th Electronic Components and Technology Conference. Buena Vista: IEEE, 2008: 67-74.
                  [15] AN P N, KOHL P A. Thermal-mechanical stress modeling of copper chip-to-substrate pillar connections[J]. IEEE Transactions on Components and Packaging Technologies,2010,33(3):621-628. DOI: 10.1109/TCAPT.2010.2050888.
                  [16] AN P N, KOHL P A. Modeling simplification for thermal mechanical analysis of high density chip-to-substrate connections[J]. Journal of Electronic Packaging,2011,133(4):041004. DOI: 10.1115/1.4005289.
                  [17] AN P, KOO H C, KOHL P. Thermomechanical modeling of all-copper chip-to-substrate connections[J]. ECS Meeting Abstracts,2010,MA2010-02:2009. DOI: 10.1149/MA2010-02/32/2009.
                  [18] SELVANAYAGAM C S, LAU J H, ZHANG X W, et al. Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps[J]. IEEE Transactions on Advanced Packaging,2009,32(4):720-728. DOI: 10.1109/TADVP.2009.2021661.
                  [19] GONG L, XU Y P, DING B, et al. Thermal management and structural parameters optimization of MCM-BGA 3D package model[J]. International Journal of Thermal Sciences,2020,147:106120. DOI: 10.1016/j.ijthermalsci.2019.106120.
                  [20] 陈高翔. 基于TSV的三维芯片热力学分析[D]. 武汉: 华中科技大学, 2018.

                  CHEN G X. Thermodynamics research of TSV based three-dimensional chip[D]. Wuhan: Huazhong University of Science and Technology, 2018.
                  [21] 王志敏, 叶贵根, 薛世峰, 等. 微针鳍散热器结构参数模拟及优化[J]. 半导体光电,2020,41(4):535-541. DOI: 10.16818/j.issn1001-5868.2020.04.017.

                  WANG Z M, YE G G, XUE S F, et al. Simulation and optimization of structural parameters of the micro pin-fin radiator[J]. Semiconductor Optoelectronics,2020,41(4):535-541. DOI: 10.16818/j.issn1001-5868.2020.04.017.
                  [22] WANG Z M, YE G G, LI X J, et al. Thermal-mechanical performance analysis and structure optimization of the TSV in 3-D IC[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology,2021,11(5):822-831. DOI: 10.1109/TCPMT.2021.3062031.
                • 加载中
                图(12) / 表(2)
                计量
                • 文章访问数:  10
                • HTML全文浏览量:  12
                • PDF下载量:  1
                • 被引次数: 0
                出版历程
                • 收稿日期:  2022-10-13
                • 修回日期:  2022-11-21
                • 网络出版日期:  2023-01-18

                目录

                  /

                  返回文章
                  返回