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                基于层★级多尺度方法的TSV晶圆翘曲≡预测模型研究

                孙国立 秦飞 代岩伟 李宝霞

                孙国立,秦飞,代岩伟,等.基于◤层级多尺度方法的TSV晶圆翘曲预≡测模型研究[J]. 微电子学与计算机,2023,40(1):130-137 doi: 10.19304/J.ISSN1000-7180.2022.0667
                引用本文: 孙国立,秦飞,代岩伟,等.基于层@级多尺度方法的TSV晶圆♀翘曲预测模型研究[J]. 微电子学与计算机,2023,40(1):130-137 doi: 10.19304/J.ISSN1000-7180.2022.0667
                SUN G L,QIN F,DAI Y W,et al. Prediction of TSV wafer warpage based on hierarchical multiscale method[J]. Microelectronics & Computer,2023,40(1):130-137 doi: 10.19304/J.ISSN1000-7180.2022.0667
                Citation: SUN G L,QIN F,DAI Y W,et al. Prediction of TSV wafer warpage based on hierarchical multiscale method[J]. Microelectronics & Computer,2023,40(1):130-137 doi: 10.19304/J.ISSN1000-7180.2022.0667

                基于层级多尺度方法的TSV晶圆翘曲预测模型研究

                doi: 10.19304/J.ISSN1000-7180.2022.0667
                基金项目: 国家自然╲科学基金(12272012);西安微电子技术研究所创新基金资助项目(771CX2020001)
                详细信息
                  作者简介:

                  孙国立:男,(1998-),硕士研究生. 研@ 究方向为电子封装技术与可靠性

                  代岩伟:男,(1988-),副教授. 研究方向为电子封装技术与可靠性研究、疲劳№断裂及结构完整性

                  李宝霞:女,(1977-),副总工艺师,博士生导》师. 研究方向为TSV三维立体集成封装⊙技术

                  通讯作者:

                  男,(1965-), 教授, 博士生导师. 研究方向为微电子封装技术与可靠性研究.E-mail:qfei@bjut.edu.cn

                • 中图分类号: TN

                Prediction of TSV wafer warpage based on hierarchical multiscale method

                • 摘要:

                  随着电子封装技术的发展,以晶圆级封装为代表的先进封装技术对集成密度、封装尺寸,及其制造和服役可靠性提出了更高的要求. TSV晶圆封装结构具有典型的结构多尺度特征,这对♀有限元模型的建立带来很大挑战. 为此,本文⌒提出了一种层级多尺度方法,并验证了所提方法的有效性. 围绕上述研究内容,首先,阐明了层级多尺度方法的原理和计算流程;其次采用层级多尺度方法建立了不同TSV晶圆〗封装工艺下的有限元模型,模拟研究了TSV转接板工艺制程中晶圆的翘曲演化,并与实验结果相对比;最后,研究了分区数量对层级多尺度方▲法精度的影响. 研究结果表明,计算规模相当情况下,随着分区数量的增加,计算误差明显降低. 与实验结果的对比表明,该方法有相对较高的晶圆翘曲预测精度. 此外,本文发展的层级多尺度方法具有一定的可移植性,可以应用到其它同类具有多尺度特征的封装〒结构可靠性分析中,为解决大规模晶圆级封装翘曲预测问题提供了一种新的解决思路.

                   

                • 图 1  TSV晶圆封装结构

                  Figure 1.  The packaging structure of TSV wafer

                  图 2  层级多尺度方法分析流程

                  Figure 2.  Analysis process of hierarchical multiscale method

                  图 3  四分之一有限元模型

                  Figure 3.  Quarter finite element model

                  图 4  基于层级多尺度方法的生死单元模拟过程

                  Figure 4.  Simulation process of element birth and death technology based on hierarchical multiscale method

                  图 5  各载荷步对应的工艺温度

                  Figure 5.  Process temperature corresponding to each load step

                  图 6  等效模型

                  Figure 6.  Equivalent model

                  图 7  全网格模型

                  Figure 7.  Full meshed model

                  图 8  等效模型与全网格模型Z向位↘移对比

                  Figure 8.  Comparison of Z-directional displacement of equivalent model and the full meshed model

                  图 9  工╱艺过程中TSV晶圆翘曲演化

                  Figure 9.  TSV wafer warpage evolution during the process

                  图 10  解键合后晶圆翘曲测量值

                  Figure 10.  Wafer warpage measurement after debonding process

                  图 11  分区数量对晶圆翘曲值的影响

                  Figure 11.  Effect of the number of partitions on wafer warpage evolution

                  图 12  分区数量对ξ预测精度的影响

                  Figure 12.  Impact of the number of partitions on prediction accuracy

                  表  1  封装结构〓尺寸参数

                  Table  1.   Dimensions of packaging structure

                  结构几何尺寸结构几何尺寸
                  Wafer晶圆8吋PI2厚度15 μm
                  Wafer厚度730 μmTSV高度200 μm
                  转接板长×宽32.66 mm×25.16 mmSiO2厚度2.5 μm
                  PI1厚度5 μmBPI1/BPI2厚度15 μm
                  M1/M2厚度5 μmBM1厚度5 μm
                  下载: 导出CSV

                  表  2  TSV转接板主要工艺制程

                  Table  2.   Main process of TSV interposer

                  工艺步
                  1刻蚀晶圆,TSV孔径20 μm,TSV刻蚀
                  深度200 um,TSV开孔率0.23%
                  2室温下正面RDL1电镀Cu,厚度5±1.5 μm,
                  RDL1金属ξ 覆盖率57%
                  3正面PI1(阻焊层)图形化,PI1(阻焊层)
                  厚度10±2 um,PI1(阻焊层)固◇化最高温度为210℃
                  4正面RDL2电镀Cu,厚度5±1.5 μm,
                  RDL2金属覆盖率19.26%
                  5正面PI2(阻焊层)图形化,PI2(阻焊层)
                  厚度15±3 um,PI2(阻焊层)固化最高温度为210℃
                  6背面键合至↓另一片玻璃晶圆,键〓合胶厚度
                  80-100 μm,固『化条件温度为210℃
                  7背面旋涂¤并图形化PI胶,烘①烤固化后形成阻焊层,
                  固化最高温度仍为210℃
                  8背面旋涂并图形化PI胶,烘烤固化后形成
                  阻焊层BPI1,厚度15 μm,固化温度210℃
                  9激◣光解键合,切割晶圆
                  下载: 导出CSV

                  表  3  材料参数[17-18]

                  Table  3.   Material properties

                  材料弹性模量/GPa泊松比CTE/
                  (ppm/℃)
                  玻璃转化
                  温度/℃
                  玻璃73.60.233.5/
                  1170.3517/
                  1310.32.8/
                  二氧化硅76.70.20.6/
                  临时键合胶1.2(E1)/
                  0.4(E2)
                  0.3845(CTE1)/
                  90(CTE2)
                  120
                  聚酰亚胺2.50.2854/
                  下载: 导出CSV

                  表  4  TSV转接板功能层和各区域含铜率

                  Table  4.   TSV interposer functional layer and copper content in each area

                  图形区测试区1测试区2测试区3
                  TSV层0.78%0.74%0.73%0.35%
                  M1层77.23%45.00%11.20%11.00%
                  PI1层0.48%1.20%0.60%2.10%
                  M2层24.43%16.00%11.20%6.00%
                  PI2层3.76%5.00%8.85%5.70%
                  BPI1层0.14%1.00%2.00%2.00%
                  BM1层24.31%13.00%11.20%11.00%
                  BPI2层9.58%10.00%5.30%5.30%
                  下载: 导出CSV

                  表  5  等效材料参数

                  Table  5.   Equivalent material properties

                  方向弹性模量
                  /GPa
                  泊松比剪切模量
                  /GPa
                  CTE/
                  (ppm/℃)
                  TSV层z130.890.3050.332.90
                  x,y130.880.3050.322.92
                  M1层z90.930.043.9817.23
                  x,y10.240.363.7732.82
                  PI1层z3.040.230.9847.25
                  x,y2.510.310.9657.92
                  M2层z30.470.031.2819.29
                  x,y3.290.381.1957.22
                  PI2层z6.800.111.0130.09
                  x,y2.600.370.9564.14
                  BPI1层z2.660.260.9851.72
                  x,y2.500.290.9755.42
                  BM1层z30.330.031.2819.31
                  x,y3.280.381.1957.28
                  BPI2层z13.470.061.0822.31
                  x,y2.760.381.0063.33
                  下载: 导出CSV
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                出版历程
                • 收稿日期:  2022-10-26
                • 修回日期:  2022-12-03
                • 网络出版日期:  2023-01-18

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