大面积处理芯片嵌入式微流体♀冷却技术

杨宇驰; 吕佩珏; 杜建宇; 李沫潼; 杨宇东; 潘鹏辉; 郑德印; 张驰; 吴道伟; 王玮

doi:10.19304/J.ISSN1000-7180.2022.0765

大面积处理芯片嵌入式微流体冷却技术

doi: 10.19304/J.ISSN1000-7180.2022.0765

1.
北京大学集成电路学院, 北京 100871
2.
清华大学航天◣航空学院, 北京 100084
3.
西安微电子技术研究所, 陕西西安 710054

详细信息

作者简介:
杨宇驰：男,（1996-）,博士研究生. 研究方向为大功率芯片的热管理技术

吕佩珏：女,（1999-）,硕士研究生. 研究方向为嵌入式微流体冷却∴可靠性

杜建宇：男,（1998-）,博士研究生. 研究方向◆为小热点热管理技术

李沫潼：女,（1998-）,博士研究生. 研究方向为工程热物理

杨宇东：男,（1991-）,博士研究生. 研究方向为三维堆叠结构热管理技术

潘鹏辉：男,（1984-）,博士研究生. 研究方向为三维封装工艺开发

郑德印：男,（1990-）,博士. 研究方向为自输运蒸发冷却√技术

张驰：女,（1991-）,博士. 研究方向为微孔结构散热的开发和表征

吴道伟：男,（1982-）,博士. 研究方向为三维封装工艺整合

王玮：男,（1977-）,博士,教授. 研究方向为芯片热管理技术. E-mail：w.wang@pku.edu.cn

中图分类号: TP302;TN406
计量
- 文章访问︻数: 11
- HTML全文浏览量: 11
- PDF下载量: 0
- 被引次数: 0
出版历程
- 收稿日期: 2022-11-22
- 修回日期: 2022-12-16
- 网络→出版日期: 2023-01-18

Embedded microfluidic cooling technology for large-area processing chips

1.
College of Integrated Circuit, Peking University, Beijing 100871, China
2.
Department of Engineering Mechanics, Tsinghua University, Beijing 100084, China
3.
Xi’an Microelectronics Technology Institute, Xi’an 710054, China

摘要

摘要:
随着集成电路制程趋于极限,登纳德缩放■定律逐步失效,芯片的功率密度逐渐提升,尤其是在5G、物联网以及高性能计算快速发展的驱动下,单芯片面积也在增大,热耗散问题日趋严重,传统的冷却方式已无法保证芯片的可靠工作. 将热沉制备在芯片内部可以避免封装材料的导热热阻▼和多层界面热阻,提升冷却性能和冷却效率. 学术界针对芯片的嵌入式微流体冷却开展了大量卓有成效的研究和探索,不断提出新型通道结构设计方案,包括平行长直通道、歧管通道、射流通道等. 旨在于优化泵功和热阻,在小压降下实现高效】冷却. 然而,随着芯片面积的增大,在限域空间实现高效冷却将更加困难,工艺难度和制造成本限制了嵌入式液冷的大规模商业化使用,目前在实际IC芯片内演示的冷却方案验◎证了嵌入式】冷却的性能,但复杂度高,兼容性差,冷却性能有待进一步提升. 尤其是在3D封装架构下,需要提出兼容小型化、高密度封装的通道结构,通过协同设计,在保证电学互连的前提下实现层间冷却. 在优化通道结构设计的同时,还需要简化工艺,降低成本,提升嵌入式微流体冷却的工艺可靠性和长期工作可靠性,才能推进嵌入式微流体冷却技术的实际应用.
- 嵌入式液冷 /
- 微流体冷却 /
- 大面积芯片 /
- 嵌入式冷却可靠性
Abstract:
As the integrated circuit process reaches the limit, Dennard's scaling law gradually fails, and the power density of the chip continues to grow. Especially driven by the rapid development of 5G, the Internet of Things and high-performance computing, the single-chip area is increasing rapidly, and the thermal dissipation problem is becoming more serious. The traditional cooling method cannot guarantee the reliability of chip operation. Embedded cooling can avoid the thermal resistance of the packaging material and the multilayer interface, which can also improve the cooling performance and efficiency. Much fruitful research and exploration have been carried out in academia on embedded microfluidic cooling of chips. New channel structure design solutions are constantly proposed, such as parallel long straight channels, manifold channels, jet channels, etc. It is designed to optimize pump power and thermal resistance for efficient cooling at small pressure drops. However, with the increased chip size, achieving efficient cooling in the restricted space will be more difficult. The process difficulty and manufacturing cost limit the large-scale commercial use of embedded liquid cooling. The current cooling scheme demonstrated in the actual IC chip verifies the performance of embedded cooling. Still, these cases have high complexity and poor compatibility, and cooling performance needs to be further improved. In particular, with 3D packaging architecture, it is necessary to propose a channel structure compatible with miniaturization and high-density packaging to achieve inter-layer cooling through electrical-thermal co-design. While optimizing the channel structure design, it is also necessary to simplify the process, reduce costs and improve the process reliability and long-term operational reliability of embedded microfluidic cooling to advance the practical application of embedded microfluidic cooling technology.
- Embedded liquid cooling /
- microfluidic cooling /
- large-area chips /
- reliability of embedded cooling

HTML全文

图 1 过去52年集成芯片内晶☉体管数量^{[1- 2]}

Figure 1. Number of transistors in integrated chips over the last 52 years

下载: 全尺〇寸图片幻灯片

图 2 芯片时钟频率/热设计功耗随时间发展^[4]

Figure 2. Chip clock speed and thermal design power consumption evolves over time

下载: 全尺寸〖图片幻灯片

图 3 芯片常规封装ㄨ结构

Figure 3. Conventional chip package structure

下载: 全尺ζ　寸图片幻灯片

图 4 嵌入式平行长直通道^[18]

Figure 4. Embedded straight parallel microchannels

下载: 全尺々寸图片幻灯片

图 5 流道结构及参数设计^[19-20]

Figure 5. Channel structure and parameter design

下载: 全尺¤寸图片ㄨ幻灯片

图 6 直通道3D模型^[23]

Figure 6. 3D model of the straight channels

下载: 全尺№寸图片▆ 幻灯片

图 7 交错间断菱形鳍片结构及其温升情况^[24]

Figure 7. Staggered interrupted diamond fin structure and the temperature rise

下载: 全尺寸图〇片幻灯片

图 8 多种扰流柱结构及其流∩阻^[30]

Figure 8. Multiple fin structures and their flow resistance

下载: 全尺寸图』片幻灯片

图 9 最大热阻随芯片面积而增大^[30]

Figure 9. Maximum thermal resistance increases with chip area

下载: 全尺㊣寸图片幻灯片

图 10 歧管结构流道及其流动截面图^[32]

Figure 10. Manifold channel and the flow cross section

下载: 全尺＠寸图片幻灯片

图 11 歧管通道3D模型^[33]

Figure 11. 3D model of manifold channels

下载: 全尺寸图⊙片幻灯片

图 12 分布式射流冷板设计★结构和实物图^[34]

Figure 12. Distributed jet cold plate design structure and physical diagram

下载: 全尺¤寸图片幻灯片

图 13 侧向供液歧管结构^[37]

Figure 13. Lateral fluid supply manifold structure

下载: 全尺寸图片幻灯片

图 14 3D歧管结构^[38]

Figure 14. 3D manifold structure

下载: 全尺寸图片幻灯片

图 15 多层歧管式微流体冷却通道阵列♀的示意图^[39]

Figure 15. Schematic diagram of a multi-layer manifold microfluidic cooling channel array

下载: 全尺寸图片幻灯片

图 16 多层硅基歧管结构^[40]

Figure 16. Multi-layer silicon-based manifold structure

下载: 全尺寸图片幻灯片

图 17 不同类型的歧管结构^{[41- 42]}

Figure 17. Different types of manifold structures

下载: 全尺寸图片幻灯片

图 18 歧管通道结♀构^[43]

Figure 18. Manifold channel structure

下载: 全尺寸图片幻灯片

图 19 嵌入式冷却加工流程以及通道◥结构和封装结构^[46]

Figure 19. Embedded cooling processing and channel / package structures

下载: 全尺寸图片幻灯片

图 20 放射状∴流道刻蚀及封装结构^[47]

Figure 20. Radiolucent channel etching and packaging structures

下载: 全尺寸图片幻灯片

图 21 协同设计工艺流程及全波整流器件^[48]

Figure 21. Co-design processing and full-wave rectifier devices

下载: 全尺寸图片幻灯片

图 22 冷却模型及实物照【片^[53]

Figure 22. Cooling model and photos

下载: 全尺寸图片幻灯片

图 23 3D冷却方案示意图与TSV光学照片^[54]

Figure 23. Schematic of 3D cooling solution and optical photos of TSV

下载: 全尺寸图片幻灯片

图 24 3D堆叠嵌入式冷却结构与堆叠后的光学图像^[55]

Figure 24. 3D stacked embedded cooling structure and optical image after stacking

下载: 全尺寸图片幻灯片

图 25 硅基扇出型嵌入式微流体冷却结构^[56]

Figure 25. Embedded silicon based fan-out microfluidic cooling structure

下载: 全尺寸图片幻灯片

图 26 TSV电容与高度的关系和高深宽比TSV结构^[59]

Figure 26. TSV capacitance vs. height and high ratio TSV structure

下载: 全尺寸图片幻灯片

图 27 不同直径的粒子轨迹仿真^[60]

Figure 27. Simulation of particle trajectories with different diameters

下载: 全尺寸图片幻灯片

图 28 压力分布与通道结构的关系^[57]

Figure 28. Relationship between pressure distribution and channel structure

下载: 全尺寸图片幻灯片

图 29 不同出入/液口ω结构的应力分布⁶¹

Figure 29. Stress distribution for different inlet and outlet/liquid port structures

下载: 全尺寸图片幻灯片

表 1 常见的TIM及其界面热阻值^[10]

Table 1. Common TIM and their interface thermal resistance

TIM	界面热阻 K·cm²/W	热通量极限 W/cm²(ΔT=60 K)	备注
导热油脂	0.2~1	300	粘度高
橡胶垫	1~3	60	固体聚合硅橡胶
相变材料	0.3~0.7	200	以蜡为主
导热胶	0.15~1	400	含填充料的环氧或硅酮
金属焊料	0.05~0.1	1200	一般用于首层〗贴装

下载: 导出CSV

参考文献(64)

[1]	Wikipedia[2022-03-09] (2022-11-20)[EB/OL]. .
[2]	ROSER M, RITCHIE H, MATHIEU E. Advances in computational technology[2022-03-30] (2022-11-20) [EB/OL]. 2022. .
[3]	DENNARD R H, GAENSSLEN F H, YU W N, et al. Design of ion-implanted MOSFET's with very small physical dimensions[J]. IEEE Journal of Solid-State Circuits,1974,9(5):257-268. DOI: 10.1109/JSSC.1974.1050511.
[4]	List of CPU power dissipation figures[2022-10-03] (2022-11-20)[EB/OL]. .
[5]	Intel. Intel^® Core^TM i9-13900K Processor 36M Cache, up to 5.80 GHz[EB/OL]. Pacific.
[6]	NVIDIA. GeForce RTX 40 Series[2022-09-21] (2022-11-20)[EB/OL]. .
[7]	AMD. AMD Instinct^TM MI250X drivers & support[2021-08-11] (2022-11-20)[EB/OL]. .
[8]	GOMES W, KOKER A, STOVER P, et al. Ponte vecchio: a multi-tile 3D stacked processor for exascale computing[C]//2022 IEEE International Solid- State Circuits Conference. San Francisco: IEEE, 2022: 42-44.
[9]	PAL S, PETRISKO D, BAJWA A A, et al. A case for packageless processors[C]//2018 IEEE International Symposium on High Performance Computer Architecture. Vienna: IEEE, 2018: 466-479.
[10]	BLAZEJ D. Thermal interface materials[EB/OL]. (2003-11-01). .
[11]	GRAEF M. More than moore white paper[C]//2021 IEEE International Roadmap for Devices and Systems Outbriefs. Santa Clara: IEEE, 2021.
[12]	LU J I Q, ROSE K, VITKAVAGE S. 3D Integration: why, what, who, when?[J]. FUTURE FAB International, 2007（23）: 27.
[13]	BAR-COHEN A. Gen-3 thermal management technology: role of microchannels and nanostructures in an embedded cooling paradigm[J]. Journal of Nanotechnology in Engineering and Medicine,2013,4(2):020907. DOI: 10.1115/1.4023898.
[14]	KANDLIKAR S G. Fundamental issues related to flow boiling in minichannels and microchannels[J]. Experimental Thermal and Fluid Science,2002,26(2-4):389-407. DOI: 10.1016/S0894-1777(02)00150-4.
[15]	Convective Heat Transfer Coefficient[2019-11-15] (2022-11-20)[EB/OL]. .
[16]	BERGLES A E, KANDLIKAR S G. On the nature of critical heat flux in microchannels[J]. Journal of Heat Transfer,2005,127(1):101-107. DOI: 10.1115/1.1839587.
[17]	PRAJAPATI Y K, BHANDARI P. Flow boiling instabilities in microchannels and their promising solutions – A review[J]. Experimental Thermal and Fluid Science,2017,88:576-593. DOI: 10.1016/j.expthermflusci.2017.07.014.
[18]	TUCKERMAN D B, PEASE R F W. High-performance heat sinking for VLSI[J]. IEEE Electron Device Letters,1981,2(5):126-129. DOI: 10.1109/EDL.1981.25367.
[19]	KNIGHT R W, GOODLING J S, HALL D J. Optimal thermal design of forced convection heat sinks-analytical[J]. Journal of Electronic Packaging,1991,113(3):313-321. DOI: 10.1115/1.2905412.
[20]	KNIGHT R W, HALL D J, GOODLING J S, et al. Heat sink optimization with application to microchannels[J]. IEEE Transactions on Components, Hybrids, and Manufacturing Technology,1992,15(5):832-842. DOI: 10.1109/33.180049.
[21]	PENG X F, PETERSON G P, WANG B X. Frictional flow characteristics of water flowing through rectangular microchannels[J]. Experimental Heat Transfer,1994,7(4):249-264. DOI: 10.1080/08916159408946484.
[22]	WANG Z H, WANG X D, YAN W M, et al. Multi-parameters optimization for microchannel heat sink using inverse problem method[J]. International Journal of Heat and Mass Transfer,2011,54(13-14):2811-2819. DOI: 10.1016/j.ijheatmasstransfer.2011.01.029.
[23]	RYU J H, CHOI D H, KIM S J. Numerical optimization of the thermal performance of a microchannel heat sink[J]. International Journal of Heat and Mass Transfer,2002,45(13):2823-2827. DOI: 10.1016/S0017-9310(02)00006-6.
[24]	KISHIMOTO T, SASKI S. Cooling characteristics of diamond-shaped interrupted cooling fin for high-power LSI devices[J]. Electronics Letters,1987,23(9):456-457. DOI: 10.1049/el:19870328.
[25]	LEE Y J, LEE P S, CHOU S K. Enhanced microchannel heat sinks using oblique fins[C]//ASME 2009 InterPACK Conference collocated with the ASME 2009 Summer Heat Transfer Conference and the ASME 2009 3rd International Conference on Energy Sustainability. San Francisco: ASME, 2010: 253-260.
[26]	JOHN T J, MATHEW B, HEGAB H. Parametric study on the combined thermal and hydraulic performance of single phase micro pin-fin heat sinks part I: square and circle geometries[J]. International Journal of Thermal Sciences,2010,49(11):2177-2190. DOI: 10.1016/j.ijthermalsci.2010.06.011.
[27]	WONG K C, LEE J H. Investigation of thermal performance of microchannel heat sink with triangular ribs in the transverse microchambers[J]. International Communications in Heat and Mass Transfer,2015,65:103-110. DOI: 10.1016/j.icheatmasstransfer.2015.04.011.
[28]	MOHAMMED H A, GUNNASEGARAN P, SHUAIB N H. Numerical simulation of heat transfer enhancement in wavy microchannel heat sink[J]. International Communications in Heat and Mass Transfer,2011,38(1):63-68. DOI: 10.1016/j.icheatmasstransfer.2010.09.012.
[29]	WOODCOCK C, YU X F, PLAWSKY J, et al. Piranha Pin Fin (PPF) - Advanced flow boiling microstructures with low surface tension dielectric fluids[J]. International Journal of Heat and Mass Transfer,2015,90:591-604. DOI: 10.1016/j.ijheatmasstransfer.2015.06.072.
[30]	BRUNSCHWILER T, MICHEL B, ROTHUIZEN H, et al. Interlayer cooling potential in vertically integrated packages[J]. Microsystem Technologies,2009,15(1):57-74. DOI: 10.1007/s00542-008-0690-4.
[31]	ARJUN K S, KUMAR R. Optimization of micro pin-fin heat sink with staggered arrangement[J]. Thermal Science,2018,22(6):2919-2931. DOI: 10.2298/TSCI161221202A.
[32]	HARPOLE G M, ENINGER J E. Micro-channel heat exchanger optimization[C]//1991 Proceedings, Seventh IEEE Semiconductor Thermal Measurement and Management Symposium. Phoenix: IEEE, 1991: 59-63.
[33]	夏国栋, 刘青, 王敏, 等. 岐管式微通█道冷却热沉的三维数值优化[J]. 工程热物理学报,2006,27(1):145-147. DOI: 10.3321/j.issn:0253-231X.2006.01.046. XIA G D, LIU Q, WANG M, et al. Three-dimensional numerical optimization of the manifold microchannel heat sink[J]. Journal of Engineering Thermophysics,2006,27(1):145-147. DOI: 10.3321/j.issn:0253-231X.2006.01.046.
[34]	BRUNSCHWILER T, ROTHUIZEN H, FABBRI M, et al. Direct liquid jet-impingment cooling with micron-sized nozzle array and distributed return architecture[C]//Thermal and Thermomechanical Proceedings 10th Intersociety Conference on Phenomena in Electronics Systems, 2006. ITHERM 2006. San Diego: IEEE, 2006: 196-203.
[35]	HAN Y, LAU B L, ZHANG X W. Package-level microjet-based hotspot cooling solution for microelectronic devices[J]. IEEE Electron Device Letters,2015,36(5):502-504. DOI: 10.1109/LED.2015.2417152.
[36]	HAN Y, LAU B L, TANG G Y, et al. Heat dissipation improvement with diamond heat spreader on hybrid Si micro-cooler for GaN devices[C]//2015 IEEE International Conference on Electron Devices and Solid-State Circuits. Singapore: IEEE, 2015: 603-606.
[37]	ESCHER W, MICHEL B, POULIKAKOS D. A novel high performance, ultra thin heat sink for electronics[J]. International Journal of Heat and Fluid Flow,2010,31(4):586-598. DOI: 10.1016/j.ijheatfluidflow.2010.03.001.
[38]	JUNG K W, KHARANGATE C R, LEE H, et al. Embedded cooling with 3D manifold for vehicle power electronics application: single-phase thermal-fluid performance[J]. International Journal of Heat and Mass Transfer,2019,130:1108-1119. DOI: 10.1016/J.IJHEATMASSTRANSFER.2018.10.108.
[39]	DRUMMOND K P, BACK D, SINANIS M D, et al. A hierarchical manifold microchannel heat sink array for high-heat-flux two-phase cooling of electronics[J]. International Journal of Heat and Mass Transfer,2018,117:319-330. DOI: 10.1016/J.IJHEATMASSTRANSFER.2017.10.015.
[40]	BACK D, DRUMMOND K P, SINANIS M D, et al. Design, fabrication, and characterization of a compact hierarchical manifold microchannel heat sink array for two-phase cooling[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology,2019,9(7):1291-1300. DOI: 10.1109/TCPMT.2019.2899648.
[41]	LUO Y, ZHANG J Z, LI W. A comparative numerical study on two-phase boiling fluid flow and heat transfer in the microchannel heat sink with different manifold arrangements[J]. International Journal of Heat and Mass Transfer,2020,156:119864. DOI: 10.1016/j.ijheatmasstransfer.2020.119864.
[42]	LIN Y H, LUO Y, LI W, et al. Single-phase and two-phase flow and heat transfer in microchannel heat sink with various manifold arrangements[J]. International Journal of Heat and Mass Transfer,2021,171:121118. DOI: 10.1016/j.ijheatmasstransfer.2021.121118.
[43]	YANG Y C, DU J Y, LI M T, et al. Embedded microfluidic cooling with compact double H type manifold microchannels for large-area high-power chips[J]. International Journal of Heat and Mass Transfer,2022,197:123340. DOI: 10.1016/j.ijheatmasstransfer.2022.123340.
[44]	STEINKE M E, KANDLIKAR S G. Single-phase heat transfer enhancement techniques in microchannel and minichannel flows[C]//ASME 2004 2nd International Conference on Microchannels and Minichannels. Rochester: ASME, 2004: 141-148.
[45]	LIU Y, CUI J, LI W Z, et al. Effect of surface microstructure on microchannel heat transfer performance[J]. Journal of Heat Transfer,2011,133(12):124501. DOI: 10.1115/1.4004594.
[46]	SARVEY T E, ZHANG Y, CHEUNG C, et al. Monolithic integration of a micropin-fin heat sink in a 28-nm FPGA[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology,2017,7(10):1617-1624. DOI: 10.1109/TCPMT.2017.2740721.
[47]	SCHULTZ M D, PARIDA P R, GAYNES M, et al. Microfluidic two-phase cooling of a high power microprocessor part A: design and fabrication[C]//2017 16th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems. Orlando: IEEE, 2017: 450-457.
[48]	VAN ERP R, SOLEIMANZADEH R, NELA L, et al. Co-designing electronics with microfluidics for more sustainable cooling[J]. Nature,2020,585(7824):211-216. DOI: 10.1038/s41586-020-2666-1.
[49]	VADDINA K R, RAHMANI A M, LATIF K, et al. Thermal modeling and analysis of advanced 3D stacked structures[J]. Procedia Engineering,2012,30:248-257. DOI: 10.1016/j.proeng.2012.01.858.
[50]	BAEK I G, PARK C J, JU H, et al. Realization of vertical resistive memory (VRRAM) using cost effective 3D process[C]//2011 International Electron Devices Meeting. Washington: IEEE, 2011: 737-740.
[51]	LAU J H, YUE T G. Thermal management of 3D IC integration with TSV (Through silicon via)[C]// 2009 59th Electronic Components and Technology Conference. San Diego: IEEE, 2009: 624-640.
[52]	FODOR A, CHINDRIS G, PITICA D, et al. Guidelines on thermal management solutions for modern packaging technologies - a review[C]//2015 IEEE 21st International Symposium for Design and Technology in Electronic Packaging. Brasov: IEEE, 2015: 41-44.
[53]	BRUNSCHWILER T, PAREDES S, DRECHSLER U, et al. Heat-removal performance scaling of interlayer cooled chip stacks[C]//2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems. Las Vegas: IEEE, 2010.
[54]	DANG B, BAKIR M S, SEKAR D C, et al. Integrated microfluidic cooling and interconnects for 2D and 3D chips[J]. IEEE Transactions on Advanced Packaging,2010,33(1):79-87. DOI: 10.1109/TADVP.2009.2035999.
[55]	ZHENG L, ZHANG Y, ZHANG X C, et al. Silicon interposer with embedded microfluidic cooling for high-performance computing systems[C]//2015 IEEE 65th Electronic Components and Technology Conference. San Diego: IEEE, 2015: 828-832.
[56]	王玮, 杨宇驰, 杜建宇. 一种硅基扇出型封装结〖构及其制备方法: 中国, ZL202110557585.7[P]. [2021-05-21] (2022-11-20). WANG W, YANG Y C, DU J Y. An embedded silicon fan-out packaging structure and the preparation method: China, ZL202110557585.7[P]. [2021-05-21] (2022-11-20).
[57]	XIA Y M, REN K L, MA S L, et al. Process development and characterization for integrating microchannel into TSV Interposer[C]//2016 IEEE 66th Electronic Components and Technology Conference. Las Vegas: IEEE, 2016: 2487-2493.
[58]	ALTMAN D H, GUPTA A, TYHACH M. Development of a diamond microfluidics-based intra-chip cooling technology for GaN[C]//ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels. San Francisco: ASME, 2015: 1-7.
[59]	SARVEY T E, ZHANG Y, ZHANG Y, et al. Thermal and electrical effects of staggered micropin-fin dimensions for cooling of 3D microsystems[C]//Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems. Orlando: IEEE, 2014: 205-212.
[60]	DITRI J, HAHN J, CADOTTE R, et al. Embedded cooling of high heat flux electronics utilizing distributed microfluidic impingement jets[C]//ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels. San Francisco: ASME, 2015: 1-10.
[61]	DU J Y, YANG Y C, YU H Q, et al. Inlet/outlet induced failures during flip-chip bonding of large area chip with embedded microchannels[C]//2022 IEEE 72nd Electronic Components and Technology Conference. San Diego: IEEE, 2022: 1805-1810.
[62]	VAN ERP R, KAMPITSIS G, MATIOLI E. Efficient microchannel cooling of multiple power devices with compact flow distribution for high power-density converters[J]. IEEE Transactions on Power Electronics,2020,35(7):7235-7245. DOI: 10.1109/TPEL.2019.2959736.
[63]	CHEN C, HOU F Z, MA R, et al. Design, integration and performance analysis of a lid-integral microchannel cooling module for high-power chip[J]. Applied Thermal Engineering,2021,198:117457. DOI: 10.1016/j.applthermaleng.2021.117457.
[64]	COLGAN E G, FURMAN B, GAYNES M, et al. A practical implementation of silicon microchannel coolers for high power chips[J]. IEEE Transactions on Components and Packaging Technologies,2007,30(2):218-225. DOI: 10.1109/TCAPT.2007.897977.